The present invention relates generally to integrated circuit testing, and more particularly to a method and apparatus for non-contact testing and diagnosing of inaccessible open integrated circuit connections.
Integrated circuit assemblies are ubiquitous in modern electronic devices, and a large portion of the industrial sector is devoted to the design and manufacture of such devices. As electronic devices are continually being improved and becoming more sophisticated, so are consumers' expectations for the level of quality of these products. Accordingly, new and improved testing techniques are continuously being sought by manufacturers to test the quality of integrated circuits, printed circuit boards, and integrated circuit assemblies after manufacture and prior to shipment of these devices. While testing entails checking many aspects of the product, such as functionality testing and burn-in testing, one of the most important tests after manufacture is basic continuity testing—that is, testing to ensure that all connections that are supposed to be connected between components of the device (e.g., integrated circuit pins to printed circuit boards, integrated circuit lead wires to pins, traces connections between printed circuit board nodes, etc.) are intact.
One common defect often uncovered during continuity testing is known as an “open” defect. In an open defect, an electrical connection is missing between two points in the circuit where electrical continuity should exist. Open defects typically result from problems in the manufacturing process, such as missing solder due to uneven application of solder paste, the unintentional introduction of particles in the wetting process, etc. Thus, during continuity testing of integrated circuit assemblies, connection defects such as open solder joints are diagnosed.
Detection of open defects is often performed using well-known capacitive lead-frame sensing technologies. For example, U.S. Pat. No. 5,557,209 to Crook et al, U.S. Pat. No. 5,498,964 to Kerschner et al., U.S. Pat. No. 5,420,500 to Kerschner, U.S. Pat. No. 5,254,953 to Crook et al., and U.S. Pat. No. 5,124,660 to Cilingiroglu, all of which are hereby incorporated by reference for all that they teach, describe techniques for detecting opens between integrated circuit signal pins and the mounting substrate (typically a printed circuit board). In other related art, U.S. Patent Application Serial Number UNKNOWN, entitled “Methods And Apparatus For Non-Contact Testing And Diagnosing Open Connections” to Parker et al., filed on Apr. 28, 2004, and assigned to the assignee of interest herein provides a method for testing for open power and ground connections in connectors and sockets, by making use of the inherently available coupling capacitors that exist between connector pins. When a signal pin is tested that is coupled to a nearby ground pin, an open on that ground pin will cause the signal pin measurement to rise in value.
For better understanding of the invention, a brief introduction to capacitive lead frame testing techniques is now presented. Turning to the drawings, FIG. 1A shows the traditional setup and FIG. 1B shows the equivalent circuit model of capacitive lead-frame testing for open signal pins on an integrated circuit.
As shown, an integrated circuit (IC) die 18 is packaged in an IC package 12. The package 12 includes a lead frame 14 supporting a plurality of pins 10a, 10b. Pads of the IC die 18 are connected to the package pins 10a, 10b at the lead frame 14 via bond wires 16a, 16b. The pins 10a, 10b are supposed to be conductively attached, for example by way of solder joints, to pads 8a, 8b of a printed circuit board (PCB) 6. The test setup shown in FIG. 1A determines whether package pins are properly connected to the board at the solder joints. The test setup includes an alternating current (AC) source 2 that applies an AC signal, through a test probe 4a, to a node connected to the pad 8a on the PCB 6 to which a pin under test 10a should be electrically connected. In a typical test environment, the AC signal is typically ten kilohertz (10 kHz) at 0.2 volts. A capacitive sensing probe 20 comprising a conductive sense plate 22 and amplifying buffer 24 is placed on top of the integrated circuit package 12. The capacitive sensing probe 20 is connected to a current measuring device 26, such as an ammeter. Another pin 10b of the integrated circuit 12 is connected to a circuit ground via a grounded probe 4b. 
When the test is performed, the AC signal applied to pad 8a appears on the pin 10a of the integrated circuit package 12. Through capacitive coupling, in particular a capacitance Csense formed between the lead frame 14 and sense plate 22, a current Is flows to the sense plate 22 and then through the amplifying buffer 24 to the current measuring device 26. If the measured current Is falls between predetermined limits, then the pin 10a is properly connected to the pad 8a. If the pin 10a is not connected to the pad 8a, a capacitance Copen is formed between the pad 8a and pin 10a, altering the current Is measured by the current measuring device 26 such that the measured current Is falls outside the predetermined limits, thereby indicating that an open defect is present at the pin connection.
In some cases, however, for example due to an excess of number of nodes on the device under test to be tested relative to the number of tester interface pins, some nodes on the device under test may be “inaccessible” to the tester for testing during a given test. Therefore, it would be desirable to have a capacitive lead-frame technique for detecting open defects on inaccessible, or otherwise non-probed, nodes of an electrical device under test.